Discuss the impact of Instruction format size on the performance of the digital systems with the help of an example?

Instruction format:

When the assembler processes an instruction or operation, it changes the instruction from its mnemonics (pronounce nemonics) to standard machine language format termed the “Instruction format”. In the method of exchange, the assembler needs to define the type of the instruction, change symbolic labels and explicit notation to a base/displacement format, ascertain the limits of specific operands and parse any literal and constant.

The instruction format size affects the execution of the digital systems. We can know the result of instruction format size as the following example.

For Example:

Consider we have the following expressions:

Z = 16(C+58)-10(A-B)

We can implement the above equation by different instruction format which is as follows:

Now we will analyze the above various instruction formats.

For this we will assume the following for over comparison:

A single byte is used for the op-code.
The size of the memory address space is 16Mbytes (Megabytes).
A single addressable memory unit is a byte.
The size of operands is 24 bit (3-bytes).
Data bus size is 8 bit (1-byte).

Now by given regarding values we will write the opcode, destination, sources and by this, we will write the numbers of bytes accessed from memory so:

3-Address Instruction:

We call this instruction format “3-Address Instruction” because here we use 3-different addresses mean’s here one is a destination and the other two are sources so.

Code size = 1+3+3+3 = 10 bytes

The number of bytes accessed from memory is 10-bytes for instruction fetch + 6-bytes for source operand fetch + 3-bytes for storing destination operand.

So, Total = 10+6+3 = 19 bytes.

2-Address Instruction:

We call this instruction format “2-Address Instruction” because here we use 2-different addresses means one is a destination and another one is source 2 because here destination acts as source 1. As we can see the code in a given previous table, we can take any of the instructions e.g., “Add y, 56” which means “y=C+56” so here source 1 is stored in ‘y’ already by instruction “LOAD y, C” which after becomes destination (as well as source 1). For easy understanding we can take example e.g., Add A, B (which is coding in Assembly) here its mean “A = A+B” so Now:

Code Size = 1+3+3 = 7-bytes.

The number of bytes accessed from memory is 7-bytes for instruction fetch + 6-bytes for source-operand fetch + 3-bytes for storing destination operand.

So, Total = 7+6+3 = 16-bytes.

1-Address Instruction:

Same like 3-Address and 2-Address Instruction, we call it “1-Address Instruction” because here we only have 1-Address which act as source 2 here we do not have any destination separately because here we use opcodes in such a way that will store the source 2 value automatically in the memory or any register.

For example, the Instruction format for 1-Address is shown in the previous table; e.g., “LDA A” means “LOAD Accumulator with value in A”, so here we can see that we can write accumulator in such a way that destination will automatically specify. So

Code Size = 1+3 = 4-bytes

The number of bytes accessed from memory is 4-bytes for instruction fetch + 3-bytes for source operand fetch + 0-bytes for storing destination operand.

So Total = 4+3+0 = 7-bytes.

0-Address Instruction:

In 0-Address Instruction we can’t use any register e.g., Accumulator or x, y, s, etc to store of temporary values we use here stack by this we push and pop overvalues and perform the operation by only using op-code; not any sources or destination mention directly so that’s why we call a “0-Address Instruction” we can also see 0-Address Instruction in the previous table.

Code Size = 1-byte

The number of bytes accessed from memory is 1-byte for instruction fetch + 6-bytes for source operand fetch + 3-bytes for storing destination operand.

So Total = 1+6+3 = 10-bytes

Now after getting the code size and the number of bytes accessed from the memory of each instruction format, we compare each of the instructions as follows:

As we know the execution of any digital system depends upon the instruction format size; means the total number of bytes obtained from memory. Remember that! “The greater number of bytes obtained from RAM or memory will impact the CPU performance also but if we obtain less no. of bytes from RAM or memory the CPU performance will increase and vice versa.

This is because of the speed gap between RAM and CPU which affects digital system performance. If the CPU accesses the RAM for performing operations large no. of time, then more CPU cycles or instructions are wasted due to the speed gap between CPU and RAM. If we talk about the 19th-century speed gap between CPU and RAM; in 1986 CPU cycles or instruction wasted 1.5 cycles.

In 1988 it increases to 5.8 cycles, in 1991 it’s 11.65, in 1994 its 26 cycles, in 1996 its 33 cycles but today’s processor wastes almost all of its cycles because if we talk about today’s modern processor which is recently launched is “Intel core i9-10900K 20M cache, up to 5.30 GHz” while the RAM of today which is recently launched is “DDR4-3200W, Memory Clock: 400MHz I/O Bus clock: 1600MHz” so we can see it a hug speed gap between CPU and RAM (CPU are in GHz while RAM has in MHz speed) which means when CPU wants to access the RAM for any operation/task its wastes most of the cycles (maybe almost all) which effects on digital performance more.

According to the instruction format comparison table, the 1-address scheme has performed better performance because here CPU accessed the bytes from RAM is less as compared to other instructions.

So, the digital system performance is better when we use that addressing scheme whose reduces then it will increase the CPU performance or digital system performance.

Questions:

Discuss the impact of Instruction format size on the performance of the digital systems with the help of an example?
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Discuss the fundamental design metrics of digital circuits in terms of the level of abstraction. suggest optimizations.
Based on the given state diagram please design the FSM?